As the demand for increasing the circuit densities of VLSI products continues to grow, it becomes imperative to more precisely control the physical size of both the active and inactive components with greater precision. The current technology has progressed to the extent that it is now possible to form integrated circuit chips having hundreds of thousands of components on chip areas only a few millimeters square. See, for example, T. Ohzone, J. Yasui, T. Ishihara and S. Horiuchi, "An 8K.times.8 Bit Static MOS RAM Fabricated by n-MOS/n-Well CMOS Technology", IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 5, Oct. 1980, pp. 854-861. Ingenious methods have been employed not only to reduce the size of the components, but also to form multilayer devices which are carefully designed to increase the packing density on the chips.
In the foregoing circuits, particularly in the form of memory cells, polysilicon resistors are now commonly used, because of their compatibility with monolithic silicon technology and the wide range of resistance values which can be achieved. See particularly N. C. Lu, L. Gerzberg, C.-Y. Lu, and J. D. Meindl, "Modeling and Optimization of Monolithic Polycrystalline Silicon Resistor", IEEE Transactions on Electron Devices, Vol. ED-28, No. 7, July 1981, pp. 818-830. Such resistors are easily fabricated, generally atop of the polysilicon gate of the MOS field effect transistors or in the isolation regions of bipolar transistors. In the fabrication of the memory cells or other devices incorporating polysilicon transistors, particularly as dimensions become more and more critical, certain problems become apparent. Firstly, because of the grain size of polysilicon and the high concentration gradient of the polysilicon layer with respect to contiguous areas, the lateral diffusion of dopants during the high temperature fabrication steps is greater than desired. In order to compensate for this diffusion, it is necessary to increase the distance between the polysilicon resistor and its neighbording components, thereby decreasing circuit density. Another approach to minimize this problem is to form barriers around the resistor with materials such as silicon nitride or thermally grown polysilicon oxide, thereby promoting process control and resistor reliability. But this approach complicated manufacture. Still further, the lateral diffusion problem makes resistivity difficult to control. To overcome these problems, much theoretical and practical work has been done to better understand the physical and electrical properties of polysilicon. See J. Seto, "The Electrical Properties of Polycrystalline Silicon Films", J. Appl. Phys., Vol. 46, No. 12, Dec. 1975, pp. 5247-5254; J. Seto, "Annealing Characteristics of Boron- and Phosphorus-Implanted Polycrystalline Silicon", J. Appl. Phys., Vol. 47, No. 12, Dec. 1976, pp. 5167-5170; G. Baccarani, B. Ricco and G. Spadini, "Transport Properties of Polycrystalline Silicon Films", J. Appl. Phys., Vol. 49, No. 11, Nov. 1978, pp. 5565-5570; and T. Yoshihara, A. Yasuoka, and H. Abe, "Conduction Properties of Chemically Deposited Polycrystalline Silicon", J. Electrochem. Soc., Vol. 127, No. 7, July 1980, pp. 1603-7. Despite these extensive studies, the aforesaid problems have not been adequately resolved.
FIG. 1 illustrates the cross-section of a conventionally fabricated polysilicon resistor. This structure consists of a p-type silicon substrate 2, a field oxide layer 4, an n+ region 3, and a phosphorosilicate glass layer (PSG) 5. In addition, regions A and B define a polysilicon layer, region B being the resistor region. These regions are formed by first doping the entire polysilicon layer to establish an initial bulk conductivity of polysilicon which corresponds to the desired low conductivity of the resistor. Generally, this would be a doping concentration of less than 2.times.10.sup.16 /cm.sup.3. Thereafter, the resistor region B is masked with a protective resistor oxide and region A is again exposed to a doping agent to render it highly conductive. The final doping concentration in region A is at least 5.times.10.sup.19 /cm.sup.3. Junctions 7 represent the lateral boundaries of the regions. (The conventional procedure used in the prior art to form polysilicon resistors is exemplified in Texas Instruments U.S. Pat. No. 4,139,786; Intel U.S. Pat. No. 4,178,674; and EMM Semi U.S. Pat. No. 4,214,917, the latter of which discusses the undesirability of dopant migration.)
In order to limit the diffusion of the dopants and to ensure good process control for resistivity, the silicon nitride layers 10 are deposited to isolate the polysilicon resistor region B from the PSG 5 and the field oxide layer 4.